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general description the max7318 2-wire-interfaced expander provides 16- bit parallel input/output (i/o) port expansion for smbus and i 2 c applications. the max7318 consists of input port registers, output port registers, polarity inversion registers, configuration registers, and an i 2 c-compatible serial interface logic compatible with smbus. the sys- tem master can invert the max7318 input data by writing to the active-high polarity inversion register. any of the 16 i/o ports can be configured as an input or output. a power-on reset (por) initializes the 16 i/os as inputs. three address select pins configure one of 64 slave id addresses. the max7318 supports hot insertion. all port pins, the int output, sda, scl, and the slave address inputs ad0? remain high impedance in power-down (v+ = 0v) with up to 6v asserted upon them. the max7318 is available in 24-pin so, ssop, tssop, and thin qfn packages and is specified over the -40? to +125? automotive temperature range. for applications requiring an smbus timeout function, refer to the max7311 data sheet. applications servers raid systems industrial control medical equipment plcs instrumentation and test measurement features ? 400kbps i 2 c-compatible serial interface ? 2v to 5.5v operation ? 5.5v overvoltage-tolerant i/os ? supports hot insertion ? 16 i/o pins that default to inputs on power-up ? 100k pullup on each i/o ? open-drain interrupt output ( int ) ? noise filter on scl/sda inputs ? 64 slave id addresses available ? low standby current (5.4 a typ) ? polarity inversion ? 4mm ? 4mm, 0.8mm thin qfn package ? -40? to +125? operation max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection ________________________________________________________________ maxim integrated products 1 ordering information 19-3381; rev 3; 12/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. smbus is a trademark of intel corp. evaluation kit available part temp range pin-package pkg code max7318awg -40? to +125? 24 wide so max7318aag -40? to +125? 24 ssop max7318atg -40? to +125? 24 thin qfn (4mm ? 4mm) t2444-4 max7318aug -40? to +125? 24 tssop top view 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v+ sda scl ad0 i/o0 ad2 ad1 i/o15 i/o14 i/o13 i/o12 i/o4 i/o3 i/o2 i/o1 16 15 14 13 9 10 11 12 i/o11 i/o10 i/o9 i/o8 gnd i/o7 i/o6 i/o5 tssop/ssop/so max7318 int thin qfn max7318atg 19 20 21 22 12 3456 18 17 16 15 14 13 23 24 12 11 10 9 8 7 scl v+ sda int ad2 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 ad0 i/o15 i/o13 i/o12 i/o11 ad1 i/o10 i/o8 i/o9 gnd i/o6 i/o7 i/o14 pin configurations
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v+ = 2v to 5.5v, t a = -40? to +125?, unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ................................................................-0.3v to +6v i/o0?/o15 as inputs ....................................(gnd - 0.3v) to +6v scl, sda, ad0, ad1, ad2, int ...................(gnd - 0.3v) to +6v maximum v+ current......................................................+250ma maximum gnd current ...................................................-250ma dc input current on i/o0?/o15 .......................................?0ma dc output current on i/o0?/o15 ....................................?0ma continuous power dissipation (t a = +70?) 24-pin wide so (derate 11.8mw/? above +70?) ....941mw 24-pin ssop (derate 8.0mw/? above +70?) ...........640mw 24-pin tssop (derate 12.2mw/? above +70?) .......976mw 24-pin thin qfn (derate 20.8mw/? above +70?) .1667mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter sym b o l conditions min typ max units supply voltage v+ 2.0 5.5 v v+ = 2v 24 36 v+ = 3.3v 45 62 supply current i + all i/os unloaded, f scl = 400khz v+ = 5.5v 83 124 ? v+ = 2v 4.8 12.1 v+ = 3.3v 5.4 14.4 standby current i stby all i/os unloaded, f scl = 0 v+ = 5.5v 6.4 19.4 ? power-on reset voltage v por 1.4 1.7 v scl, sda input-voltage low v il 0.3 x v+ v input-voltage high v ih 0.7 x v+ v low-level output voltage v ol i sink = 6ma 0.4 v leakage current i l -1 +1 ? input capacitance 10 pf i/o_ input-voltage low v il 0.8 v input-voltage high v ih 1.8 v input leakage current t a = -40? to +85?; includes internal pullup current, v io = v+ 1a internal pullup current t a = -40? to +85?, v io = 0 34 100 ? v+ = 2v, v ol = 0.5v 8.5 17 v+ = 3.3v, v ol = 0.5v 17 32 low-level output current i sink v+ = 5v, v ol = 0.5v 43 ma v+ = 3.3v, v oh = 2.4v 29 41 high output current i source v+ = 5v, v oh = 4.5v 31 ma ad0, ad1, ad2 input-voltage low v il 0.3 x v+ v input-voltage high v ih 0.7 x v+ v
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection _______________________________________________________________________________________ 3 note 1: all parameters are 100% production tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: a master device must internally provide a hold time of at least 300ns for the sda signal (referred to the v il of the scl signal) to bridge the undefined region scl? falling edge. note 3: c b = total capacitance of one bus line in pf. note 4: the maximum t f for the sda and scl bus lines is specified at 300ns. the maximum fall time for the sda output stage t f is specified at 250ns. this allows series protection resistors to be connected between the sda and scl pins and the sda/scl bus lines without exceeding the maximum specified t f . note 5: input filters on the sda and scl inputs suppress noise spikes less than 50ns. dc electrical characteristics (continued) (v+ = 2v to 5.5v, t a = -40? to +125?, unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter sym b o l conditions min typ max units leakage current -1 +1 ? input capacitance 4pf int low-level output current i ol v ol = 0.4v 6 ma ac electrical characteristics (v+ = 2v to 5.5v, t a = -40? to +125?, unless otherwise noted.) (note 1) parameter sym b o l conditions min typ max units scl clock frequency f scl 400 khz bus free time between stop and start conditions t buf figure 2 1.3 ? hold time (repeated) start condition t hd , sta figure 2 0.6 ? repeated start condition setup time t su,sta figure 2 0.6 ? stop condition setup time t su , sto figure 2 0.6 ? data hold time t hd , dat figure 2 (note 2) 0.9 ? data setup time t su , dat figure 2 100 ns scl low period t low figure 2 1.3 ? scl high period t high figure 2 0.7 ? v+ < 3.3v 500 sda fall time t f figure 2 (notes 3, 4) v+ 3.3v 250 ns pulse width of spike suppressed t sp (note 5) 50 ns port timing output data valid t pv figure 7 3 ? input data setup time 27 ? input data hold time 0s interrupt timing interrupt valid t iv figure 9 30.5 ? interrupt reset t ir figure 9 2 ?
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) supply current vs. temperature max7318 toc01 temperature ( c) supply current ( a) 100 75 25 50 0 -25 10 20 30 40 50 60 70 80 90 100 0 -50 125 f scl = 400khz all i/os unloaded v+ = 3.3v v+ = 5v v+ = 2v standby supply current vs. temperature max7318 toc02 temperature ( c) supply current ( a) 100 75 25 50 0 -25 2 4 6 8 10 12 0 -50 125 scl = v+ all i/os unloaded v+ = 5v v+ = 3.3v v+ = 2v supply current vs. supply voltage max7318 toc03 supply voltage (v) supply current ( a) 5.0 4.5 3.5 4.0 3.0 2.5 10 20 30 40 50 60 70 80 90 100 0 2.0 5.5 f scl = 400khz all i/os unloaded i/o sink current vs. output low voltage max7318 toc04 v ol (v) i sink (ma) 0.5 0.4 0.3 0.2 0.1 2 4 6 8 10 12 14 16 18 20 22 24 0 0 0.6 v+ = 2v t a = +125 c t a = +25 c t a = -40 c i/o sink current vs. output low voltage max7318 toc05 v ol (v) i sink (ma) 0.5 0.4 0.3 0.2 0.1 5 10 15 20 25 30 35 40 45 50 0 0 0.6 v+ = 3.3v t a = +125 c t a = -40 c t a = +25 c i/o sink current vs. output low voltage max7318 toc06 v ol (v) i sink (ma) 0.4 0.3 0.2 0.1 5 10 15 20 25 30 35 40 45 50 0 0 0.5 v+ = 5v t a = +125 c t a = -40 c t a = +25 c i/o output low voltage vs. temperature max7318 toc07 temperature ( c) v ol (mv) 100 75 -25 0 25 50 50 100 150 200 250 300 350 400 0 -50 125 v+ = 5v, i sink = 10ma v+ = 2v, i sink = 10ma v+ = 2v, i sink = 1ma v+ = 5v, i sink = 1ma i/o source current vs. output high voltage max7318 toc08 v+ - v oh (v) i source (ma) 0.6 0.5 0.4 0.3 0.2 0.1 5 10 15 20 25 0 0 0.7 v+ = 2v t a = +125 c t a = +25 c t a = -40 c i/o source current vs. output high voltage max7318 toc09 v+ - v oh (v) i source (ma) 0.6 0.5 0.3 0.4 0.2 0.1 5 10 15 20 25 30 35 40 45 50 0 0 0.7 v+ = 3.3v t a = +125 c t a = +25 c t a = -40 c
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection _______________________________________________________________________________________ 5 pin description typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) i/o source current vs. output high voltage max7318 toc10 v+ - v oh (v) i source (ma) 0.6 0.5 0.3 0.4 0.2 0.1 5 10 15 20 25 30 35 40 45 50 0 0 v+ = 5v t a = +125 c t a = +25 c t a = -40 c i/o high voltage vs. temperature max7318 toc11 temperature ( c) v+ - v oh (v) 100 75 50 25 0 -25 100 200 300 400 500 0 -50 125 v+ = 5v, i source = 10ma v+ = 2v, i source = 10ma pin tssop/ ssop/so thin qfn name function 122 int interrupt output (open drain) 2 23 ad1 address input 1 3 24 ad2 address input 2 4?1 1? i/o0?/o7 input/output port 1 12 9 gnd supply ground 13?0 10?7 i/o8?/o15 input/output port 2 21 18 ad0 address input 0 22 19 scl serial clock line 23 20 sda serial data line 24 21 v+ supply voltage. bypass with a 0.047? capacitor to gnd. ep exposed pad on package underside. connect to gnd.
max7318 detailed description the max7318 general-purpose input/output (gpio) peripheral provides up to 16 i/o ports, controlled through an i 2 c-compatible serial interface. the max7318 consists of input port registers, output port registers, polarity inversion registers, and configuration registers. upon power-on, all i/o lines are set as inputs. three slave id address select pins, ad0, ad1, and ad2, choose one of 64 slave id addresses, including the eight addresses supported by the phillips pca9555. table 1 is the register address table. tables 2? show detailed register information. serial interface serial addressing the max7318 operates as a slave that sends and receives data through a 2-wire interface. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master, typically a microcon- troller, initiates all data transfers to and from the max7318, and generates the scl clock that synchro- nizes the data transfer (figure 2). 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 6 _______________________________________________________________________________________ i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 input/output port 1 smbus control 8 bit read pulse write pulse i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 input/output port 2 8 bit read pulse write pulse int power-on reset input filter n v+ sda scl ad2 ad1 ad0 gnd max7318 figure 1. block diagram scl sda start condition stop condition repeated start condition start condition t su,dat t hd,dat t low t hd,sta t high t r t f t su,sta t hd,sta t su,sto t buf figure 2. 2-wire serial interface timing diagram
each transmission consists of a start condition sent by a master, followed by the max7318 7-bit slave address plus r/ w bit, a register address byte, 1 or more data bytes, and finally a stop condition (figure 3). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 4). acknowledge the acknowledge bit is a clocked 9th bit, which the recipient uses as a handshake receipt of each byte of data (figure 5). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is sta- ble low during the high period of the clock pulse. when the master is transmitting to the max7318, the max7318 max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection _______________________________________________________________________________________ 7 sda scl s start condition p stop condition figure 3. start and stop conditions sda scl data line stable; data valid change of data allowed figure 4. bit transfer scl sda by transmitter clock pulse for acknowledgment start condition sda by receiver 12 89 s figure 5. acknowledge
max7318 generates the acknowledge bit since the max7318 is the recipient. when the max7318 is transmitting to the master, the master generates the acknowledge bit. slave address the max7318 has a 7-bit-long slave address (figure 6). the 8th bit following the 7-bit slave address is the r/ w bit. set this bit low for a write command and high for a read command. slave address pins ad2, ad1, and ad0 choose 1 of 64 slave id addresses (table 7). data bus transaction the command byte is the first byte to follow the 8-bit device slave address during a write transmission (table 1, figure 7). the command byte is used to deter- mine which of the following registers are written or read. writing to port registers transmit data to the max7318 by sending the device slave address and setting the lsb to a logic zero. the command byte is sent after the address and deter- mines which registers receive the data following the command byte (figure 7). 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 8 _______________________________________________________________________________________ sda sda a6 a5 a4 a3 a2 a1 a0 msb lsb ack r/w programmable figure 6. slave address command byte address (hex) function protocol power-up default 0x00 input port 1 read byte xxxx xxxx 0x01 input port 2 read byte xxxx xxxx 0x02 output port 1 read/write byte 1111 1111 0x03 output port 2 read/write byte 1111 1111 0x04 port 1 polarity inversion read/write byte 0000 0000 0x05 port 2 polarity inversion read/write byte 0000 0000 0x06 port 1 configuration read/write byte 1111 1111 0x07 port 2 configuration read/write byte 1111 1111 0xff factory reserved. (do not write to this register.) table 1. command-byte register 123456789 scl sda s a0000001 76543210a 76543210a 0a slave address command byte port 1 data port 2 data r/w acknowledge from slave acknowledge from slave start condition acknowledge from slave acknowledge from slave t pv t pv write to port data out port 1 read from port 2 figure 7. writes to output registers through write-byte protocol
the max7318? eight registers are configured to oper- ate as four register pairs: input ports, output ports, polarity inversion ports, and configuration ports. after sending 1 byte of data to one register, the next byte is sent to the other register in the pair. for example, if the first byte of data is sent to output port 2, then the next byte of data is stored in output port 1. an unlimited number of data bytes can be sent in one write transmis- sion. this allows each 8-bit register to be updated inde- pendently of the other registers. reading port registers to read the device data, the bus master must first send the max7318 address with the r/ w bit set to zero, fol- lowed by the command byte, which determines which register is accessed. after a restart, the bus master must then send the max7318 address with the r/ w bit set to 1. data from the register defined by the com- mand byte is then sent from the max7318 to the master (figures 8, 9). max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection _______________________________________________________________________________________ 9 s 0 a a s 1 a a na p slave address slave address msb data lsb msb data lsb command byte r/w r/w acknowledge from slave acknowledge from slave acknowledge from slave master transmitter becomes master receiver and slave receiver becomes slave transmitter data from lower or upper byte of register data from lower or upper byte of register transfer of data can be stopped at any time by a stop condition. figure 8. read from register 123456789 scl slave address port 1 data port 2 data port 1 data port 2 data s17777 00001p a a a a r/w acknowledge from slave acknowledge from master acknowledge from master acknowledge from master nonacknowledge from master t iv t ir read from port 1 read from port 2 data into port 1 data into port 2 int transfer of data can be stopped anytime by a stop condition. when the stop condition occurs, data present at the last acknowledge phase is valid (output mode) and command byte has previously been set to register 00. figure 9. read from input registers
max7318 data is clocked into a register on the falling edge of the acknowledge clock pulse. after reading the first byte, additional bytes may be read and reflect the content in the other register in the pair. for example, if input port 1 is read, the next byte read is input port 2. an unlimited number of data bytes can be read in one read trans- mission, but the final byte received must not be acknowledged by the bus master. interrupt ( int ) the open-drain interrupt output, int, activates when one of the port pins changes states and only when the pin is configured as an input. the interrupt deactivates when the input returns to its previous state or the input register is read (figure 9). a pin configured as an out- put does not cause an interrupt. each 8-bit port register is read independently; therefore, an interrupt caused by port 1 is not cleared by a read of port 2? register. changing an i/o from an output to an input may cause a false interrupt to occur if the state of that i/o does not match the content of the input port register. input/output port when an i/o is configured as an input, fets q1 and q2 are off (figure 10), creating a high-impedance input with a nominal 100k pullup to v+. all inputs are overvoltage protected to 5.5v, independent of supply voltage. when a port is configured as an output, either q1 or q2 is on, depending on the state of the output port register. when v+ powers up, an internal power-on reset sets all regis- ters to their respective defaults (table 1). input port registers the input port registers (table 2) are read-only ports. they reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the respective configuration register. a read of the input port 1 register latches the current value of i/o0?/o7. a read of the input port 2 register latches the current value of i/o8?/o15. writes to the input port registers are ignored. 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 10 ______________________________________________________________________________________ d set q clr q d set q clr q data from shift register write configuration pulse data from shift register write pulse read pulse output port register d set q clr q polarity inversion register polarity register data d set q clr q input port register configuration register q1 q2 100k data from shift register write polarity pulse power-on reset to int input port register data gnd v dd i/o pin output port register data figure 10. simplified schematic of i/os
output port registers the output port registers (table 3) set the outgoing logic levels of the i/os defined as outputs by the respective configuration register. reads from the output port registers reflect the value that is in the flip-flop con- trolling the output selection, not the actual i/o value. polarity inversion registers the polarity inversion registers (table 4) enable polarity inversion of pins defined as inputs by the respective port configuration registers. set the bit in the polarity inversion register to invert the corresponding port pin? polarity. clear the bit in the polarity inversion register to retain the corresponding port pin? original polarity. configuration registers the configuration registers (table 5) configure the directions of the i/o pins. set the bit in the respective configuration register to enable the corresponding port as an input. clear the bit in the configuration register to enable the corresponding port as an output. standby the max7318 goes into standby when the i 2 c bus is idle. standby supply current is typically 5.4?. applications information hot insertion the i/o ports i/o0?/o15, interrupt output int , and serial interface sda, scl, ad0? remain high impedance with up to 6v asserted on them when the max7318 is pow- ered down (v+ = 0v). the max7318 can therefore be used in hot-swap applications. note that each i/o? 100k pullup effectively becomes a 100k pulldown when the max7318 is powered down. power-supply consideration the max7318 operates from a supply voltage of 2v to 5.5v. bypass the power supply to gnd with a 0.047? capacitor as close to the device as possible. for the qfn version, connect the exposed pad to gnd. max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection ______________________________________________________________________________________ 11 i7 i6 i5 i4 i3 i2 i1 i0 bit i15 i14 i13 i12 i11 i10 i9 i8 table 2. registers 0x00, 0x01?nput port registers o7 o6 o5 o4 o3 o2 o1 o0 bit o15 o14 o13 o12 o11 o10 o9 o8 power-up default 1 1111111 table 3. registers 0x02, 0x03?utput port registers i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 bit i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 power-up default 0 0000000 table 4. registers 0x04, 0x05?olarity inversion registers i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 bit i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 power-up default 1 1 1 1 1 1 1 1 table 5. registers 0x06, 0x07?onfiguration registers
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 12 ______________________________________________________________________________________ ad2 ad1 ad0 a6 a5 a4 a3 a2 a1 a0 address (hex) gndsclgnd0010000 0x20 gndsclv+0010001 0x22 gndsdagnd0010010 0x24 gndsdav+0010011 0x26 v+sclgnd0010100 0x28 v+sclv+0010101 0x2a v+sdagnd0010110 0x2c v+sdav+0010111 0x2e gndsclscl0011000 0x30 gndsclsda0011001 0x32 gndsdascl0011010 0x34 gndsdasda0011011 0x36 v+sclscl0011100 0x38 v+sclsda0011101 0x3a v+sdascl0011110 0x3c v+sdasda0011111 0x3e gndgndgnd0100000 0x40 gndgndv+0100001 0x42 gndv+gnd0100010 0x44 gndv+v+0100011 0x46 v+gndgnd0100100 0x48 v+gndv+0100101 0x4a v+v+gnd0100110 0x4c v+v+v+0100111 0x4e gndgndscl0101000 0x50 gndgndsda0101001 0x52 gndv+scl0101010 0x54 gndv+sda0101011 0x56 v+gndscl0101100 0x58 v+gndsda0101101 0x5a v+v+scl0101110 0x5c v+v+sda0101111 0x5e table 6. max7318 address map
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection ______________________________________________________________________________________ 13 ad2 ad1 ad0 a6 a5 a4 a3 a2 a1 a0 address (hex) sclsclgnd1010000 0xa0 sclsclv+1010001 0xa2 sclsdagnd1010010 0xa4 sclsdav+1010011 0xa6 sdasclgnd1010100 0xa8 sdasclv+1010101 0xaa sdasdagnd1010110 0xac sdasdav+1010111 0xae sclsclscl1011000 0xb0 sclsclsda1011001 0xb2 sclsdascl1011010 0xb4 sclsdasda1011011 0xb6 sdasclscl1011100 0xb8 sdasclsda1011101 0xba sdasdascl1011110 0xbc sdasdasda1011111 0xbe sclgndgnd1100000 0xc0 sclgndv+1100001 0xc2 sclv+gnd1100010 0xc4 sclv+v+1100011 0xc6 sdagndgnd1100100 0xc8 sdagndv+1100101 0xca sdav+gnd1100110 0xcc sdav+v+1100111 0xce sclgndscl1101000 0xd0 sclgndsda1101001 0xd2 sclv+scl1101010 0xd4 sclv+sda1101011 0xd6 sdagndscl11011 00 0xd8 sdagndsda1101101 0xda sdav+scl1101110 0xdc sdav+sda1101111 0xde table 6. max7318 address map (continued) chip information transistor count: 12,994 process: bicmos
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 14 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicw.eps package outline, .300" soic 1 1 21-0042 b rev. document control no. approval proprietary information title: top view front view max 0.012 0.104 0.019 0.299 0.013 inches 0.291 0.009 e c dim 0.014 0.004 b a1 min 0.093 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.35 2.35 min 0.49 0.30 max 2.65 0.050 0.016 l 0.40 1.27 0.512 0.496 d d min dim d inches max 12.60 13.00 millimeters min max 20 ac 0.447 0.463 ab 11.75 11.35 18 0.398 0.413 aa 10.50 10.10 16 n ms013 side view h 0.419 0.394 10.00 10.65 e 0.050 1.27 d 0.614 0.598 15.20 24 15.60 ad d 0.713 0.697 17.70 28 18.10 ae h e n d a1 b e a 0-8 c l 1 variations:
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection ______________________________________________________________________________________ 15 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 16 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 i
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection ______________________________________________________________________________________ 17 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection 18 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max7318 2-wire-interfaced, 16-bit, i/o port expander with interrupt and hot-insertion protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/04 initial release 1 2 3 12/07 corrected error in general description ; various style edits; updated tssop and tqfn package outlines. 1, 15, 16

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